In general, bus systems are employed for conducting interface operations for data and control signals between various functional devices in computing or data processing apparatuses. For example, a system-on-a-chip (SOC) usually comprises a bus system for interconnecting functional blocks in operation. It is desirable to develop bus systems that are inexpensive and comprise non-complex frameworks.
A typical bus system, as shown in FIG. 1, generally comprises a bus (1), a bus arbiter (2), and a plurality of bus masters (BM0˜BMn−1) and bus slaves (BS0˜BSn−1). A bus master can read/write data from/to a desired one of the bus slaves, when the bus master sends a bus request to the arbiter (2) and is granted bus ownership by the bus arbiter (2). The bus (1) occupation is limited one access per request. The bus slaves are not able to request access to the bus (1), but merely respond to requests from a bus master by reading data or by writing data to the bus (1). The bus arbiter (2) grants bus ownership to the bus master having the highest priority, when multiple bus requests are received by the arbiter (2).
There are various types of bus masters that may be embedded in SOCs. For instance, bus masters include central processor units (CPUs), general-purpose direct memory access (DMA) controllers, dedicated direct memory access (DMA) controllers, etc. Examples of bus slaves are external memory controllers, or universal asynchronous receiver and transmitter (UART), etc.
The type of bus arbiter that can be implemented for a given system depends, for example, on the structural features of the system and the intended application. For example, an equitable arbitration process may be used to enhance overall performances in the system by eliminating bus starvations in which some bus masters with lower priorities for bus occupation are not granted bus ownership as needed.
The techniques for arbitrating bus occupation are classified into several types, as shown in the following table, based on the rule for establishing priorities and the ability to program bus occupancies for the bus masters.
TABLE 1Priority decision ruleFixedRound-robinProgrammabilityPossible(a) Fixed(b) Fixed BusPriorityoccupation rate(1/n)Impossible(c) Adjustable(d) Adjustable BusPriorityoccupancy rate
The fixed priority (a) is the simplest method for bus arbitration, but is incapable of adjusting the priorities of bus occupation and may cause bus starvation. However, method (a) is advantageous for high-speed operation and can be implemented using a non-complex architecture. Although the arbitration method (c) provides adjustable priorities, bus starvation can still occur. With respect to the round-robin methods, the fixed bus occupation rate method (b) eliminates the problem of bus starvation that may occur using arbitration methods (a) and (c) by establishing each bus occupancy rate as 1/n for each bus master. However, the method (b) does not allow, for example, the bus occupation rate for a specific bus master to be increased when a given bus master requires more times of bus occupation than any other bus masters in a SOC system including a plurality of bus masters and slaves.
The adjustable round-robin method (d) addresses the problems associated with the methods (b) and (c), whereby bus occupation is arbitrated by dividing the bus masters into groups as shown in FIG. 2 (refer to “PCI system architecture” proposed by Tom Shanley & Don Anderson; Addision-Wesley Publishing Company, Fiurth edition). Referring to FIG. 2, the bus masters A, B, X, Y, and Z are divided into two groups, e.g., a higher-priority group HPG and a lower-priority group LPG. The group HPG includes the bus masters A and B, while the group LPG includes the bus masters X, Y, and Z. Assuming that there are consequent bus requests from the bus masters, an order for bus ownerships may be arranged as follows: A-B-X-A-B-Y-A-B-Z-A-B-X- . . . Assuming that nine bus requests have been generated by the bus masters, bus occupation rates are settled such as A= 3/9=⅓, B= 3/9=⅓, X= 1/9, Y= 1/9, and Z= 1/9. The arbitration mechanism of FIG. 2, however, has limitations in adjusting bus occupation rates for the bus masters.
The arbitration methods summarized in Table 1 can be implemented in bus systems requiring high-frequency operations. Bus arbitration methods that allow bus occupation rates to be programmed with desirable values without limitations are preferably implemented for systems such as data communications or remote communications. For instance, a time interval of bus occupancy for a selected bus master can be programmed to retain predetermined data rates assigned to the selected bus master. However, this arbitration method, although suitable for data communication systems, is problematic in systems such as SOCs where bus requests occur very dynamically at every clock cycle. In addition, such methods require complex algorithms and hardware architectures.
The benefits of controlling bus occupation rates of bus masters arise from the facts that: (1) bus masters that are functionally different may request bus occupation rates that are different (e.g., it is desirable to have different occupation rates for a 100 Mbps Ethernet module and a 120 Mbps USB module; (2) there may occur an equitable bus request by a specific bus master (e.g., a multi-channel DMA controller with a one-time bus request through a channel arbiter thereof may have a lower bus occupation rate than the others, or either the data amount or the formation of transaction data to be dealt by each bus master after obtaining a bus ownership may be variable such as single or burst); and (3) there is a need to increase or to decrease a bus occupation rate for a specific bus master in accordance with the current application system.